GATE DEPLETION ANALYSIS OF PMOSFETS WITH POLYSILICON GATE

Abstract

This paper presents the study of the polysilicon gate depletion effect (PDE) on the threshold voltage and capacitance of PMOSFETs devices. Simulation analysis over wide range of oxide thickness, gate length width and gate doping were also performed. Simulation results proved that the polysilicon gate depletion effect caused the performance degradation in MOSFET devices due to the reduction of the total gate capacitance as the potential drop of the gate increased. The PDE effect of PMOSFETs with silicon nitride (Si₃N₄) as dielectric material has been proved to have better performance than the PMOSFETs with silicon dioxide (SiO₂) dielectric. It has been found that the polysilicon gate is not compatible to High-K dielectric material.